As described in U.S. Pat No. 4,713,356 issued to Hiruta, in conventional MOSFET devices, a lot of drawbacks are present in micropatterning for high integration in integrated circuits. For instance, as the junction between source and drain regions is made shallower in order to further reduce the device size, the surface resistance of source and drain regions and the junction resistance of gate electrode increase. As a result, a significantly longer delay time for applications with the device appears. Additionally, as channel length decreases, short channel effects can occur, thereby reducing the threshold voltage of the transistor and making stable transistor characteristics difficult to be obtained. It is therefore proposed to deposit tungsten over the source and drain regions and the gate electrode in order to resolve these problems. However, a small residue of tungsten on the spacer on the sidewalls of the gate electrode and the isolation region of the device reduces the insulation properties between the gate electrode and the source and drain regions. A problem is thus created for both circuit reliability and high integration. If the tungsten attached to the spacer of the gate electrode and the isolation region of the device is etched to improve insulation properties, damages may result to the tungsten layer itself and also to the underlying substrate since the tungsten layer is only about 1,000 A, thus good contact is difficult to be obtained. Moreover, even if a device size is further reduced, the portion of the device size occupied by source and drain regions still remains large, since the size of a device region in a MOSFET is determined by the gate area and the size of source and drain regions. In addition, contact holes are conventionally formed to be separated from gate electrode in order to preserve the insulation properties between the wiring layers for the gate electrode and the source and drain regions, which results in an increase of area of the source and drain regions.
Hiruta disclosed in U.S. Pat No. 4,713,356 a method of manufacturing a MOS transistor in which the portion of the area occupied by the source and drain regions are reduced. In this prior art method, the sidewalls of a gate electrode are first selectively deposited with an insulation film, then conductive material layers are selectively formed on the source and drain regions, partially extending to the side portions of the isolation region for the device, and contact holes filled with a conductive material in an insulation protective film are formed to reach the conductive material layers for forming source and drain wiring layers after the insulation protective film is formed over the entire surface of the conductive material layers and the gate electrode. However, the contact resistance to the gate electrode and the source and drain regions are desired to be further reduced when the MOSFET is made smaller. In particular, the device provided by Hiruta cannot be formed with a metal layer on the gate electrode as in the above described prior art, resulted in that the contact resistance to the gate electrode cannot be further reduced in the device.
On the other hand, silicide to be formed on an electrode in order to reduce the electrode resistance is well known, it is therefore desired for the small device to employ a silicide on the electrode of the device to further reduce the electrode resistance thereof. However, a gate electrode with a silicide thereon cannot be obtained in the transistor provided by Hiruta, since metal gate cannot be formed in this device. It is therefore desired an improvement of electrode resistance for a MOSFET with source and drain regions reduced in size beyond lithography limit and method for making the MOSFET.